With the development of display technologies, display panels have been increasingly, widely used. Often, during operation of a display panel, a gate controlling circuit in the display panel generates scanning signals to respectively drive gate lines in an array substrate in sequence, so that a data signal can be transmitted to each of a plurality of pixel units in the array substrate. The above scanning signal is generated by a gate controlling unit having a shift register function in the gate controlling circuit.
FIG. 1 shows a circuit diagram of a gate controlling unit in the related art. As shown in FIG. 1, the gate controlling unit includes: a first N-channel Metal Oxide Semiconductor (NMOS) transistor MN1, where a gate electrode of the first NMOS transistor MN1 is electrically connected with a trigger signal input terminal SET configured for receiving a trigger signal, a source electrode of the first NMOS transistor MN1 is electrically connected with a first node P0, and a drain electrode of the first NMOS transistor MN1 is electrically connected with a first level signal input terminal VGH configured for receiving a first level signal; a second NMOS transistor MN2, where a gate electrode of the second NMOS transistor MN2 is electrically connected with a reset signal input terminal RESET configured for receiving a reset signal, a source electrode of the second NMOS transistor MN2 is electrically connected with a second level signal input terminal DIR configured for receiving a second level signal, and a drain electrode of the second NMOS transistor MN2 is electrically connected with the first node P0; a third NMOS transistor MN3, where a gate electrode of the third NMOS transistor MN3 is electrically connected with a second node Q0, a source electrode of the third NMOS transistor MN3 is electrically connected with a third level signal input terminal VGL configured for receiving a third level signal, and a drain electrode of the third NMOS transistor MN3 is electrically connected with the first node P0; a fourth NMOS transistor MN4, where a gate electrode of the fourth NMOS transistor MN4 is electrically connected with the first node P0, a source electrode of the fourth NMOS transistor MN4 is electrically connected with the third level signal input terminal VGL, and a drain electrode of the fourth NMOS transistor MN4 is electrically connected with the second node Q0; a fifth NMOS transistor MN5, where a gate electrode of the fifth NMOS transistor MN5 is electrically connected with the first node P0, a source electrode of the fifth NMOS transistor MN5 is electrically connected with an output terminal GOUT configured for generating an output signal, and a drain electrode of the fifth NMOS transistor MN5 is electrically connected with a first clock signal input terminal CKB configured for receiving a first clock signal; a sixth NMOS transistor MN6, where a gate electrode of the sixth NMOS transistor MN6 is electrically connected with the second node Q0, a source electrode of the sixth NMOS transistor MN6 is electrically connected with the third level signal input terminal VGL, and a drain electrode of the sixth NMOS transistor MN6 is electrically connected with the output terminal GOUT; a seventh NMOS transistor MN7, where a gate electrode of the seventh NMOS transistor MN7 is electrically connected with a second clock signal input terminal CK configured for receiving a second clock signal, a source electrode of the seventh NMOS transistor MN7 is electrically connected with the third level signal input terminal VGL, and a drain electrode of the seventh NMOS transistor MN7 is electrically connected with the output terminal GOUT; a first capacitor C11, where a first plate of the first capacitor C11 is electrically connected with the first clock signal input terminal CKB, and a second plate of the first capacitor C11 is electrically connected with the second node Q0; and a second capacitor C12, where a first plate of the second capacitor C12 is electrically connected with the first node P0, and a second plate of the second capacitor C12 is electrically connected with the output terminal GOUT.
The gate controlling unit of FIG. 1 has a shift register function, and can generate a scanning signal to drive a row of gate lines. A gate electrode controlling circuit, which includes cascaded gate controlling units connected in series, can drive the gate lines on the array substrate line by line. However, after a first stage gate controlling unit generates a scanning signal, the gate electrode controlling circuit continues to drive the next stage gate controlling unit. In such a case, when various in-cell touch systems (such as an in-cell capacitive screen or electromagnetic screen) are employed in such display panels, the scanning of the touch signals is synchronized with the scanning by the display signals, which may cause drawbacks such as instability of the display system, touch position reporting mistakes and poor linearity of the touch system.